openTPU, an open-source AI accelerator developed by AI agents, goes viral: full RTL/ISA/compiler stack runs Qwen3.5, Gemma 4 and a 35B MoE on a Kintex-7 FPGA card at up to 85.8 tok/s

openTPU (github.com/FeSens/openTPU, Apache-2.0) asks how far AI agents can go at hardware design and whether they can build the chip that runs their own inference. It applies the author's auto-arch-tournament method (previously used for AI-designed RISC-V cores); on Hacker News the author said the accelerator started at a few tokens per second and reached 80+ tok/s on small models through a recursive self-improvement loop. The monorepo contains SystemVerilog RTL, an ISA of 8x32-bit-word instructions, a bit-exact Python simulator that serves as the spec, a Python-embedded kernel language (@ol.jit) and compiler, host tools (otpu-chat, otpu-smi) and the Lens profiler with roofline and per-cycle timelines. The design is intentionally simple: one instruction per cycle across DMA, an int8 systolic matrix unit, an fp32 vector unit and a quantizer, with no caches or hidden scheduling. On an Inspur YPCB-00338 card (Kintex-7 xc7k480t, two DDR3-1066 channels, 17.1 GB/s peak, 133.33 MHz) it runs ten-plus real models token-for-token identical to the simulator: LFM2.5-230M at 85.8 tok/s, Qwen3-0.6B at 31.3, Qwen3.5-2B at 12.09 and Gemma 4 E2B at 12.14 tok/s (4-bit, int8 head, device decode), using 82-94% of DRAM bandwidth. MoE models larger than the card's 4 GiB stream experts from the host: Qwen3.5-35B-A3B runs at 3.95 tok/s. All numbers are self-reported in the README; there is no independent reproduction or like-for-like GPU comparison yet. Everything except the card runs on a laptop via the simulator.